TMS9900 CPU

The TMS 9900 microprocessor is a single-chip 16 bit central processing unit (CPU) produced using N channel silicon-gate MOS technology. The instruction set of the TMS 9900 includes the capabilities offered by full minicomputers. The unique memory-to-memory architecture features multiple register files, resident in memory, which allow faster response to interrupts and increased programming flexibility. The separate bus structure simplifies the system design effort.

The 9900 was released in 1976, and was used in the TI 990 minicomputer. When TI released the TI-99/4, the TMS 9900 made it the first 16-bit home computer!

KEY FEATURES OF THE TMS9900

16-Bit Instruction Word

Full Minicomputer Instruction Set Capability

Up to 65,536 Bytes of Memory

3.3 - MHz Speed

Advanced Memory-to-Memory Architecture

Separate Memory, I/O, and Interrupt-Bus Structures

16 General Registers

16 Prioritized Interrupts

Programmed and DMA I/O Capability

N-Channel Silicon-Gate Technology

A0 through A14 comprise the address bus.

This 3-state bus provides the memory

address vector to the external-memory

system when MEMEN is active and I/O-bit

address and external-instruction addresses

to the I/O system when MEMEN is inactive.

The address bus assumes the high-impedance

state when HOLDA is active.

D0 through D15 comprise the bidirectional

3-state data bus. This bus transfers memory

data to (when writing) and from (when

reading) the external-memory system when

MEMEN is active. The data bus assumes the

high-impedance state when HOLDA is

active.

Supply voltage (-5 V NOM)

Supply voltage (5 V NOM)

Supply voltage (12 V NOM)

Ground Reference

Phase-1 clock

Phase-2 clock

Phase-3 clock

Phase-4 clock

Data bus in. When active(high), DBIN indicates that the 

TMS9900 has  disbled its output buffers to allow the memory

to place memory-read data on the data bus during MEMEN. 

DBIN remains low in all other cases except when HOLDA

is active.

Memory enable.  When active (low), MEMEN indicates that

the address bus contains a memory address.

Write enable.  When active (low), WE indicates that memory

write data is available from the TMS9900 to be 

written into memory.

CRU clock.  When active (high), CRUCLK indicates that

external interface logic should sample the output data on

CRUOUT or should decode external instructions on A0-A2

CRU data in.  CRUIN, normally driven by 3-state or open

collector devices, redeives input data from external interface

logic.  When the processor executes a STCR or TB 

instruction, it samples CRUIN for the level of the CRU input

bit specified by the address bus (A3-A14).

CRU dat out.  Serial I/O data appears on the CRUOUT line 

when an LDCR, SBZ or SBO instruction is executed. The

data on CRUOUT should be sampled by external I/O interface

logic when CRUCLK goes active (high).

INTREQ

Interrupt request. When active (low), INTREQ indicates that an

external interrupt is requested. If INTREQ is active, the 

processor loads the data on the interrupt-code-lines IC0 through

IC3 into the internal interrupt-code-storage register.  The code

is copared to the interrupt mask bits of the status register. If

equal or higher priority than the enabled interrupt level

(interrupt code equal or less than status register bits 12 

through 15) the TMS9900 interrupt sequence is initiated. If

the comparsion fails, the processor ignores the request. 

INTREQ should remain active and the processor will continue

to sample IC0 through IC3 until the program enables a 

sufficiently low priority to accecpt the request interrupt.

IC0 (MSB)

Interrupt codes. IC0 is the MSB of the interrupt code, which is

IC1

sampled when INTREQ is active. When IC0 through IC3 are

IC2

LLLH, the highest external-priority interrupt is being requested

IC3 (LSB)

and when HHHH, the lowest priority interrupt is being requested.

HOLD

Hold. When active (low), HOLD indicates to the processor that

an external controller (e.g., DMA device) desires to utilize the

address and data busses to transfer data to or from memory.

The TMS9900 enters the hold state following a hold signal when

it has completed its present memory cycle. The processor

then places the address and data buses in the high-impedance

state (along with WE,MEMEN, and DBIN) and responds with a

hold-acknowledge signal (HOLDA).  When HOLD is removed

the processor returns to normal operation.

HOLDA

Hold acknowledge.  When active (high), HOLDA indicates that 

the processor is in the hold state and the address and data 

buses and memory control outputs (WE,MEMEN, and DBIN)

are in the high-impedance state.

READY

Ready.  When active (high), READY indicates that memory

will be ready to read or write during the next clock cycle.

When no-ready is indicated during a memory operation, the 

TMS9900 enters a wait state and suspends internal operation

until the memory systems indicate ready.

WAIT

Wait.  When active (high), WAIT indicates that the TMS9900

has entered a wait state because of a not-ready condition from

memory.

IAQ

Instruction acquisition. IAQ is active (high) during any memory

cycle when the TMS9900 is acquiring an instruction.  IAQ can

be used to detect illegal op codes.

LOAD

Load.  When active (low), LOAD causes the TMS9900 to 

execute a nonmaskable interrupt with memory address FFFC

containing the trap vector (WP and PC). The load sequence 

begins after the instruction being executed is completed. 

LOAD will also terminate an idle state. If LOAD is active during

the time RESET is released, then the LOAD trap will occur

after the RESET function is completed.  LOAD should remain

active for one instruction period.  IAQ can be used to determine

instruction boundaries.  This signal can be used to implement

cold-start ROM loaders.  Additionally, front-panel routines can 

be implemented using CRU bits as front-panel-interface signals

and software-control routines to control the panel operations.

RESET

Reset. When active (low), RESET causes the processor to be 

reset and inhibits WE and CRUCLK.  When RESET is released

the TMS9900 then initiates a level-zero interrupt sequence that 

acquires WP and PC from locations 0000 and 0002, sets all

status register bits to zero, and starts execution. RESET will 

also terminate an idle state.  RESET must be held active for 

a minimum of three clock cycles.